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NVIDIA

Santa Clara, California - United States
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PACKAGING TECHNICAL LEAD

Description

PACKAGING TECHNICAL LEAD #1605750 The Package Engineering Technical Lead is responsible for defining a Ball Grid Array electronic package. The candidate should be experienced in transmission line theory and practice. You will define the chip paring, interconnect scheme (to substrate), and manage the package layout design process. You will work with the system design engineer to define a ballout necessary to implement a robust electrical package. MINIMUM REQUIREMENTS: - Prior experience in board / system design or package design is preferred. - BSEE with at least 5+ years of relevant experience is required. - Tool use includes Cadence APD and Valor. Perl programming language and EXCEL familiarity are helpful. EOE

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