SENIOR SERDES DESIGN ENGINEER

Description

SENIOR SERDES DESIGN ENGINEER #1643227 Lead architecture and design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on experience in the lab with silicon validation, debugging, characterization and bring up. RESPONSIBILITIES: - Lead design and implementation of high speed interface circuit - Design projects include high speed transceivers and high frequency PLLs - Design, simulation, and verification of mixed-signal circuits - Supervise closely IC circuit/mask designers, provide floorplan and layout guidelines - Support lab characterization of silicon - Solve challenges of circuit design in deep submicron CMOS - Take designs through implementation and productization - Work with cross functional teams MINIMUM REQUIREMENTS: - BS or MS in Electrical Engineering. PhD preferred. - 8+ years of design experience in CMOS analog / mixed-signal circuit Design - Working knowledge of Cadence custom design tools, circuit simulator, timing analysis tool - A team player with good communication skills - Demonstrated experience in designing and mentoring designers - Extensive design experience in Tx, Rx, CDR, PLL for high speed IO interfaces - In-depth understanding of deep submicron CMOS process and related circuit design issues - Experience in silicon bring-up, debugging and use of lab instrumentation is required - Knowledge in system level timing budget, signal integrity, and power integrity is a plus - Experience in Verilog, Matlab, Primetime, Nanotime EOE