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Intel Corporation

Beaverton, Oregon - United States
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736200- Validation Tech Lead

Description

Validation Tech Lead - 736200 

Description

 

If you're interested in computer graphics and working with leading graphics software engineers on Intel's latest GPU/CPU architecture, then our Visual and Parallel Computing Group (VPG) has opportunities for you.VPG delivers Intel's 3D graphics, media, display GPU, and Parallel Computing Technology.

In this position, you will be playing a lead role in the pre-silicon validation of Intel's leading edge integrated graphics CPU products, with focus on integration validation of the graphics core. Your responsibilities will include, but not be limited to:

- Architecting optimized validation environments based on a thorough analysis of requirements

- Defining, implementing, and deploying verification capabilities, methodologies, and process improvements

- Development of testplans, testbench, BFMs (bus functional models), checkers, trackers, functional coverage as required

- Working closely with design engineers, micro-architects, architects, other team members to ensure high quality of testplans, validation environment, and tests

- Strong discipline and attention to detail in ensuring effective high quality validation that minimizes bug escapes to higher levels of validation

- Gaining graphics domain expertise to be able to debug efficiently and effectively at any level of validation

- Interfacing with emulation, software teams to ensure synergy with RTL validation and driving debug where applicable

- Provide mentoring to other team members on validation BKMs and debug

 

Qualifications

 

Minimum Qualifications:

You must possess a Bachelor's degree with 9 years' experience, a Master's degree with 6 years' experience, or a PhD with 4 years' experience.  Degree should be in Electrical Engineering or related field.  Experience should be in the following:

- Experience in defining, implementing and deploying verification capabilities and methodologies

- Expertise in Verilog*, SystemVerilog*, Tcl/Perl scripting, and VCS* simulator

- Strong experience with architecting optimized validation environments, testplan/testbench/bus-functional-models/checkers/trackers/functional coverage development, and test writing/debug

- Working knowledge of UNIX*, and Windows*

- Familiarity with the ASIC design flow

Preferred Qualifications:

- AVM*/OVM* knowledge

- Familiarity with 3d Graphics

 

Job Category

: Engineering 

Primary Location

: USA-California, Folsom 

Full/Part Time

Full Time

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