SENIOR POWER ESTIMATION AND MODELING ENGINEER

Description

SENIOR POWER ESTIMATION AND MODELING ENGINEER #1564978 In this role you will be leading a team responsible for architecting/developing/correlating Power Estimation Models/Tools for NVIDIA's GPU/Tegra chips. As a Power Team lead you will be interfacing with management team to understand requirements and plan the tool features, set team goals that help meet the organizational needs. RESPONSIBILITIES: - Architect and develop Power Estimation Models for Dynamic use-case, Leakage, and IO Power estimation. Design the tools based on these models, and devices/develop solid testing methodology/infrastructures. - Lead a small size team, interface/coordinate with external teams in the US and India that provides necessary input data to develop the estimation models and tools. - Interface with the management team to discuss requirements, solutions/methodologies, team plans, and priorities, including the following: * Translate higher level feature requests for Power estimation tool to executable tasks for the team; come up with verification plan and schedule. * Steer the execution to meet the schedule and do periodic well quality-assured tool release. - Correlate/Calibrate these models using measured Silicon data. - Help study/contribute to Perf/Watt improvement ideas for GPUs and system MINIMUM REQUIREMENTS: - MSEE/MSCE, preferably PhD, with specialization/experience related to Power/Performance estimation techniques. - 8 years of experience of which 2+ year in team lead role and 2+ years of hands on experience working with power estimation techniques, flows and algorithms. - Understands power basics including transistor-level leakage/dynamic characteristics of VLSI circuits. - Familiarity w/ low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) etc. is desirable. - Good software programming skills. Python/Perl/C++ preferred. Good skills with object oriented programming and design. - Good Understanding of mathematical optimization techniques is a highly desirable. - Good understanding of performance monitors/simulators used in modern processor architectures (GPU is a plus), and power estimation techniques using the same. - Exposure to lab setup including power measurements equipment such as scope/DAQ is with ability to analyze board level power issues is highly desirable. - Power analysis EDA tools such as PTPX/EPS experience is plus. EOE